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authorRichard Henderson <richard.henderson@linaro.org>2021-01-31 23:23:07 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-06-19 08:51:11 -0700
commitbcb81061dc8173076d9669f969d132b998cd2af9 (patch)
treeb8ccf116e63ea6dade7803e6ba4b0325916d2b9d /tcg
parentb6139eb0578fc422cfee77fccbd11152e73af1df (diff)
tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order
As the only call-clobbered regs for TCI, these should receive the least priority. Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/tci/tcg-target.c.inc4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 8f3f9ef7d3..d54c01b9de 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -170,8 +170,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
}
static const int tcg_target_reg_alloc_order[] = {
- TCG_REG_R0,
- TCG_REG_R1,
TCG_REG_R2,
TCG_REG_R3,
TCG_REG_R4,
@@ -186,6 +184,8 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R13,
TCG_REG_R14,
TCG_REG_R15,
+ TCG_REG_R1,
+ TCG_REG_R0,
};
#if MAX_OPC_PARAM_IARGS != 6