diff options
| author | Richard Henderson <rth@twiddle.net> | 2014-03-26 11:37:06 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-06-23 07:32:12 -0700 |
| commit | 8fa391a011a421ed8bf63385ae8e051df453c2e3 (patch) | |
| tree | 7c6f7ea0ef28f2213ccd364822eab691776e3063 /tcg | |
| parent | dfca177874efe0a66ea435bf167bde33b18f59f7 (diff) | |
tcg-ppc64: Support mulsh_i32
Tested-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 5 | ||||
| -rw-r--r-- | tcg/ppc64/tcg-target.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index a5ad14051d..02ee8e2a53 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -410,6 +410,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define OR XO31(444) #define XOR XO31(316) #define MULLW XO31(235) +#define MULHW XO31( 75) #define MULHWU XO31( 11) #define DIVW XO31(491) #define DIVWU XO31(459) @@ -2263,6 +2264,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_muluh_i32: tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); break; + case INDEX_op_mulsh_i32: + tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); + break; case INDEX_op_muluh_i64: tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); break; @@ -2329,6 +2333,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_muluh_i32, { "r", "r", "r" } }, + { INDEX_op_mulsh_i32, { "r", "r", "r" } }, #if TCG_TARGET_REG_BITS == 64 { INDEX_op_ld8u_i64, { "r", "r" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 7b90087695..066e74b9c7 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -71,7 +71,7 @@ typedef enum { #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 1 -#define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 |