diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-06-05 18:29:04 +0300 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-07-08 07:30:17 +0100 |
| commit | 623d7e3551a6fc5693c06ea938c60fe281b52e27 (patch) | |
| tree | f32537daa61ae4faa823be2e11f457eb9918e5e0 /tcg | |
| parent | 276d72ca1b9017916cadc7c170d0d6b31633a9e5 (diff) | |
util: Add cpuinfo-ppc.c
Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc/tcg-target.c.inc | 44 | ||||
| -rw-r--r-- | tcg/ppc/tcg-target.h | 16 |
2 files changed, 9 insertions, 51 deletions
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 5c8378f8f6..c866f2c997 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -101,10 +101,7 @@ #define ALL_GENERAL_REGS 0xffffffffu #define ALL_VECTOR_REGS 0xffffffff00000000ull -TCGPowerISA have_isa; -static bool have_isel; -bool have_altivec; -bool have_vsx; +#define have_isel (cpuinfo & CPUINFO_ISEL) #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG 30 @@ -3879,45 +3876,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) static void tcg_target_init(TCGContext *s) { - unsigned long hwcap = qemu_getauxval(AT_HWCAP); - unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); - - have_isa = tcg_isa_base; - if (hwcap & PPC_FEATURE_ARCH_2_06) { - have_isa = tcg_isa_2_06; - } -#ifdef PPC_FEATURE2_ARCH_2_07 - if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { - have_isa = tcg_isa_2_07; - } -#endif -#ifdef PPC_FEATURE2_ARCH_3_00 - if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { - have_isa = tcg_isa_3_00; - } -#endif -#ifdef PPC_FEATURE2_ARCH_3_10 - if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { - have_isa = tcg_isa_3_10; - } -#endif - -#ifdef PPC_FEATURE2_HAS_ISEL - /* Prefer explicit instruction from the kernel. */ - have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; -#else - /* Fall back to knowing Power7 (2.06) has ISEL. */ - have_isel = have_isa_2_06; -#endif - - if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { - have_altivec = true; - /* We only care about the portion of VSX that overlaps Altivec. */ - if (hwcap & PPC_FEATURE_HAS_VSX) { - have_vsx = true; - } - } - tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; if (have_altivec) { diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c7552b6391..9a41fab8cc 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -25,6 +25,8 @@ #ifndef PPC_TCG_TARGET_H #define PPC_TCG_TARGET_H +#include "host/cpuinfo.h" + #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) #define TCG_TARGET_NB_REGS 64 @@ -61,14 +63,12 @@ typedef enum { tcg_isa_3_10, } TCGPowerISA; -extern TCGPowerISA have_isa; -extern bool have_altivec; -extern bool have_vsx; - -#define have_isa_2_06 (have_isa >= tcg_isa_2_06) -#define have_isa_2_07 (have_isa >= tcg_isa_2_07) -#define have_isa_3_00 (have_isa >= tcg_isa_3_00) -#define have_isa_3_10 (have_isa >= tcg_isa_3_10) +#define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) +#define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) +#define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) +#define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) +#define have_altivec (cpuinfo & CPUINFO_ALTIVEC) +#define have_vsx (cpuinfo & CPUINFO_VSX) /* optional instructions automatically implemented */ #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ |