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authorAurelien Jarno <aurelien@aurel32.net>2010-04-08 11:10:48 +0200
committerAurelien Jarno <aurelien@aurel32.net>2010-04-08 11:11:21 +0200
commita175b996b2c5cbde266d0dc1e86bc2ce09fae263 (patch)
tree984f7e273e9be7551d78d839cf70d1a06d964724 /tcg
parent98926b0a25446696a4a62184f169b48e133a7a13 (diff)
tcg/ia64: fix tlb addend read
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/ia64/tcg-target.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 113f245dcb..6e69ef4b49 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1449,13 +1449,8 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg,
tcg_opc_a1 (TCG_REG_P0, OPC_ADD_A1, TCG_REG_R2,
TCG_REG_R2, TCG_AREG0));
tcg_out_bundle(s, mII,
-#if TARGET_LONG_BITS == 32
- tcg_opc_m3 (TCG_REG_P0, OPC_LD4_M3, TCG_REG_R57,
- TCG_REG_R2, offset_addend - offset_rw),
-#else
tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R57,
TCG_REG_R2, offset_addend - offset_rw),
-#endif
tcg_opc_a1 (TCG_REG_P0, OPC_AND_A1, TCG_REG_R3,
TCG_REG_R3, TCG_REG_R56),
tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,