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authorRichard Henderson <richard.henderson@linaro.org>2021-01-29 22:18:37 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-03-17 07:24:44 -0600
commitcbe871313e7e65b4e65ac5616634337ec4d9f45c (patch)
tree4fe6e81414a4dda6b402d438f3b508759aab435b /tcg
parent120402b5cba8f305470102167956d50ed1e6608b (diff)
tcg/tci: Split out tci_args_rrrr
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/tci.c16
1 files changed, 11 insertions, 5 deletions
diff --git a/tcg/tci.c b/tcg/tci.c
index 91c5f71065..2fcf5a2473 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -239,6 +239,15 @@ static void tci_args_rrrc(const uint8_t **tb_ptr,
}
#if TCG_TARGET_REG_BITS == 32
+static void tci_args_rrrr(const uint8_t **tb_ptr,
+ TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3)
+{
+ *r0 = tci_read_r(tb_ptr);
+ *r1 = tci_read_r(tb_ptr);
+ *r2 = tci_read_r(tb_ptr);
+ *r3 = tci_read_r(tb_ptr);
+}
+
static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
{
@@ -661,11 +670,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
}
break;
case INDEX_op_mulu2_i32:
- t0 = *tb_ptr++;
- t1 = *tb_ptr++;
- t2 = tci_read_rval(regs, &tb_ptr);
- tmp64 = (uint32_t)tci_read_rval(regs, &tb_ptr);
- tci_write_reg64(regs, t1, t0, (uint32_t)t2 * tmp64);
+ tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
+ tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
break;
#endif /* TCG_TARGET_REG_BITS == 32 */
#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64