diff options
| author | Alistair Francis <Alistair.Francis@wdc.com> | 2018-12-12 20:58:11 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2018-12-17 06:04:44 +0300 |
| commit | 161dec9d1b03552e78e5728186eae9cf1dfbe035 (patch) | |
| tree | f48693d33b40a41c8d10aa78940baf56c562c2dc /tcg | |
| parent | e1dcf3529d0797b25bb49a20e94b62eb93e7276a (diff) | |
tcg/mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS
Instead of hard coding 31 for the shift right use TCG_TARGET_REG_BITS - 1.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <7dfbddf7014a595150aa79011ddb342c3cc17ec3.1544648105.git.alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/mips/tcg-target.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index a06ff257fa..be0bc92e8e 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -792,7 +792,7 @@ static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); } else if (rl == al && rl == bl) { - tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31); + tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); } else { tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); |