diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-03-04 16:20:51 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-04-15 20:09:54 +0200 |
| commit | 6645c147db4bb84b1b24c49be9398be22902923b (patch) | |
| tree | 43781c1cdf21318eff2535c4cb20b05e6903ac07 /tcg | |
| parent | 6c858762de60ffff80011251b5fe1ae93cbcd2c8 (diff) | |
tcg-ppc64: Implement mulu2/muls2_i64
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 27 | ||||
| -rw-r--r-- | tcg/ppc64/tcg-target.h | 4 |
2 files changed, 29 insertions, 2 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 1018266118..0f335837b6 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1988,6 +1988,31 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, } break; + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i64: + { + int oph = (opc == INDEX_op_mulu2_i64 ? MULHDU : MULHD); + TCGReg outl = args[0], outh = args[1]; + a0 = args[2], a1 = args[3]; + + if (outl == a0 || outl == a1) { + if (outh == a0 || outh == a1) { + outl = TCG_REG_R0; + } else { + tcg_out32(s, oph | TAB(outh, a0, a1)); + oph = 0; + } + } + tcg_out32(s, MULLD | TAB(outl, a0, a1)); + if (oph != 0) { + tcg_out32(s, oph | TAB(outh, a0, a1)); + } + if (outl != args[0]) { + tcg_out_mov(s, TCG_TYPE_I64, args[0], outl); + } + } + break; + default: tcg_dump_ops (s); tcg_abort (); @@ -2116,6 +2141,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, + { INDEX_op_muls2_i64, { "r", "r", "r", "r" } }, + { INDEX_op_mulu2_i64, { "r", "r", "r", "r" } }, { -1 }, }; diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 8dff1d5490..cb77634714 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -114,8 +114,8 @@ typedef enum { #define TCG_TARGET_HAS_movcond_i64 1 #define TCG_TARGET_HAS_add2_i64 1 #define TCG_TARGET_HAS_sub2_i64 1 -#define TCG_TARGET_HAS_mulu2_i64 0 -#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_mulu2_i64 1 +#define TCG_TARGET_HAS_muls2_i64 1 #define TCG_AREG0 TCG_REG_R27 |