diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-28 15:07:41 -1000 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
commit | 2f74f45e32beb0ae24366128fdf685a5121c0f67 (patch) | |
tree | c42e7ad0532bfa98c43796ffb705d696ab44cae5 /tcg/tci | |
parent | 552672bae63dd2c470fc533f276b746bae90b813 (diff) |
tcg/tci: Remove TCG_CONST
Restrict all operands to registers. All constants will be forced
into registers by the middle-end. Removing the difference in how
immediate integers were encoded will allow more code to be shared
between 32-bit and 64-bit operations.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci')
-rw-r--r-- | tcg/tci/tcg-target-con-set.h | 6 | ||||
-rw-r--r-- | tcg/tci/tcg-target.c.inc | 85 | ||||
-rw-r--r-- | tcg/tci/tcg-target.h | 3 |
3 files changed, 22 insertions, 72 deletions
diff --git a/tcg/tci/tcg-target-con-set.h b/tcg/tci/tcg-target-con-set.h index 38e82f7535..f51b7bcb13 100644 --- a/tcg/tci/tcg-target-con-set.h +++ b/tcg/tci/tcg-target-con-set.h @@ -10,16 +10,12 @@ * tcg-target-con-str.h; the constraint combination is inclusive or. */ C_O0_I2(r, r) -C_O0_I2(r, ri) C_O0_I3(r, r, r) -C_O0_I4(r, r, ri, ri) C_O0_I4(r, r, r, r) C_O1_I1(r, r) C_O1_I2(r, 0, r) -C_O1_I2(r, ri, ri) C_O1_I2(r, r, r) -C_O1_I2(r, r, ri) -C_O1_I4(r, r, r, ri, ri) +C_O1_I4(r, r, r, r, r) C_O2_I1(r, r, r) C_O2_I2(r, r, r, r) C_O2_I4(r, r, r, r, r, r) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index aba7f75ad1..feac4659cc 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -92,8 +92,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rem_i64: case INDEX_op_remu_i32: case INDEX_op_remu_i64: - return C_O1_I2(r, r, r); - case INDEX_op_add_i32: case INDEX_op_add_i64: case INDEX_op_sub_i32: @@ -126,8 +124,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_rotl_i64: case INDEX_op_rotr_i32: case INDEX_op_rotr_i64: - /* TODO: Does R, RI, RI result in faster code than R, R, RI? */ - return C_O1_I2(r, ri, ri); + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + return C_O1_I2(r, r, r); case INDEX_op_deposit_i32: case INDEX_op_deposit_i64: @@ -135,11 +134,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: - return C_O0_I2(r, ri); - - case INDEX_op_setcond_i32: - case INDEX_op_setcond_i64: - return C_O1_I2(r, r, ri); + return C_O0_I2(r, r); #if TCG_TARGET_REG_BITS == 32 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ @@ -147,11 +142,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_sub2_i32: return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: - return C_O0_I4(r, r, ri, ri); + return C_O0_I4(r, r, r, r); case INDEX_op_mulu2_i32: return C_O2_I2(r, r, r, r); case INDEX_op_setcond2_i32: - return C_O1_I4(r, r, r, ri, ri); + return C_O1_I4(r, r, r, r, r); #endif case INDEX_op_qemu_ld_i32: @@ -294,44 +289,6 @@ static void tcg_out_r(TCGContext *s, TCGArg t0) tcg_out8(s, t0); } -/* Write register or constant (native size). */ -static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_debug_assert(const_arg == 1); - tcg_out8(s, TCG_CONST); - tcg_out_i(s, arg); - } else { - tcg_out_r(s, arg); - } -} - -/* Write register or constant (32 bit). */ -static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_debug_assert(const_arg == 1); - tcg_out8(s, TCG_CONST); - tcg_out32(s, arg); - } else { - tcg_out_r(s, arg); - } -} - -#if TCG_TARGET_REG_BITS == 64 -/* Write register or constant (64 bit). */ -static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg) -{ - if (const_arg) { - tcg_debug_assert(const_arg == 1); - tcg_out8(s, TCG_CONST); - tcg_out64(s, arg); - } else { - tcg_out_r(s, arg); - } -} -#endif - /* Write label. */ static void tci_out_label(TCGContext *s, TCGLabel *label) { @@ -419,7 +376,7 @@ static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) { uint8_t *old_code_ptr = s->code_ptr; tcg_out_op_t(s, INDEX_op_call); - tcg_out_ri(s, 1, (uintptr_t)arg); + tcg_out_i(s, (uintptr_t)arg); old_code_ptr[1] = s->code_ptr - old_code_ptr; } @@ -453,7 +410,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_setcond_i32: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); - tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; #if TCG_TARGET_REG_BITS == 32 @@ -462,15 +419,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); tcg_out_r(s, args[2]); - tcg_out_ri32(s, const_args[3], args[3]); - tcg_out_ri32(s, const_args[4], args[4]); + tcg_out_r(s, args[3]); + tcg_out_r(s, args[4]); tcg_out8(s, args[5]); /* condition */ break; #elif TCG_TARGET_REG_BITS == 64 case INDEX_op_setcond_i64: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); - tcg_out_ri64(s, const_args[2], args[2]); + tcg_out_r(s, args[2]); tcg_out8(s, args[3]); /* condition */ break; #endif @@ -516,8 +473,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */ tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); break; case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */ tcg_out_r(s, args[0]); @@ -551,8 +508,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */ tcg_out_r(s, args[0]); - tcg_out_ri64(s, const_args[1], args[1]); - tcg_out_ri64(s, const_args[2], args[2]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); break; case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */ tcg_out_r(s, args[0]); @@ -565,7 +522,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_brcond_i64: tcg_out_r(s, args[0]); - tcg_out_ri64(s, const_args[1], args[1]); + tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; @@ -599,8 +556,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */ tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); - tcg_out_ri32(s, const_args[2], args[2]); + tcg_out_r(s, args[1]); + tcg_out_r(s, args[2]); break; #if TCG_TARGET_REG_BITS == 32 case INDEX_op_add2_i32: @@ -615,8 +572,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_brcond2_i32: tcg_out_r(s, args[0]); tcg_out_r(s, args[1]); - tcg_out_ri32(s, const_args[2], args[2]); - tcg_out_ri32(s, const_args[3], args[3]); + tcg_out_r(s, args[2]); + tcg_out_r(s, args[3]); tcg_out8(s, args[4]); /* condition */ tci_out_label(s, arg_label(args[5])); break; @@ -629,7 +586,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, #endif case INDEX_op_brcond_i32: tcg_out_r(s, args[0]); - tcg_out_ri32(s, const_args[1], args[1]); + tcg_out_r(s, args[1]); tcg_out8(s, args[2]); /* condition */ tci_out_label(s, arg_label(args[3])); break; diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 8f7ed676fc..9c0021a26f 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -157,9 +157,6 @@ typedef enum { TCG_AREG0 = TCG_REG_R14, TCG_REG_CALL_STACK = TCG_REG_R15, - - /* Special value UINT8_MAX is used by TCI to encode constant values. */ - TCG_CONST = UINT8_MAX } TCGReg; /* Used for function call generation. */ |