diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2022-10-21 10:34:21 +1000 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2023-02-04 06:19:42 -1000 |
commit | 896c76e6ba5d9a3444fb8528fdc407747ecc82f2 (patch) | |
tree | 775801d8011510f2627a1ce32bf44d5e88e0d0ac /tcg/tci.c | |
parent | c4f4a00ac7d947c9b100e3cb62755a9a157df1fa (diff) |
tcg/tci: Fix big-endian return register ordering
We expect the backend to require register pairs in
host-endian ordering, thus for big-endian the first
register of a pair contains the high part.
We were forcing R0 to contain the low part for calls.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci.c')
-rw-r--r-- | tcg/tci.c | 19 |
1 files changed, 10 insertions, 9 deletions
@@ -520,26 +520,27 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, ffi_call(pptr[1], pptr[0], stack, call_slots); } - /* Any result winds up "left-aligned" in the stack[0] slot. */ switch (len) { case 0: /* void */ break; case 1: /* uint32_t */ /* + * The result winds up "left-aligned" in the stack[0] slot. * Note that libffi has an odd special case in that it will * always widen an integral result to ffi_arg. */ - if (sizeof(ffi_arg) == 4) { + if (sizeof(ffi_arg) == 8) { + regs[TCG_REG_R0] = (uint32_t)stack[0]; + } else { regs[TCG_REG_R0] = *(uint32_t *)stack; - break; } - /* fall through */ + break; case 2: /* uint64_t */ - if (TCG_TARGET_REG_BITS == 32) { - tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]); - } else { - regs[TCG_REG_R0] = stack[0]; - } + /* + * For TCG_TARGET_REG_BITS == 32, the register pair + * must stay in host memory order. + */ + memcpy(®s[TCG_REG_R0], stack, 8); break; default: g_assert_not_reached(); |