diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-29 22:36:40 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-03-17 07:24:44 -0600 |
| commit | 79dd3a4f59e88129e6887ac970f2ed794504e5d7 (patch) | |
| tree | bfe65252ea16677f23d5cb0ef9de2b007a576dd6 /tcg/tci.c | |
| parent | cbe871313e7e65b4e65ac5616634337ec4d9f45c (diff) | |
tcg/tci: Clean up deposit operations
Use the correct set of asserts during code generation.
We do not require the first input to overlap the output;
the existing interpreter already supported that.
Split out tci_args_rrrbb in the translator.
Use the deposit32/64 functions rather than inline expansion.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci.c')
| -rw-r--r-- | tcg/tci.c | 33 |
1 files changed, 16 insertions, 17 deletions
@@ -168,6 +168,7 @@ static tcg_target_ulong tci_read_label(const uint8_t **tb_ptr) * tci_args_<arguments> * where arguments is a sequence of * + * b = immediate (bit position) * c = condition (TCGCond) * i = immediate (uint32_t) * I = immediate (tcg_target_ulong) @@ -238,6 +239,16 @@ static void tci_args_rrrc(const uint8_t **tb_ptr, *c3 = tci_read_b(tb_ptr); } +static void tci_args_rrrbb(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, + TCGReg *r2, uint8_t *i3, uint8_t *i4) +{ + *r0 = tci_read_r(tb_ptr); + *r1 = tci_read_r(tb_ptr); + *r2 = tci_read_r(tb_ptr); + *i3 = tci_read_b(tb_ptr); + *i4 = tci_read_b(tb_ptr); +} + #if TCG_TARGET_REG_BITS == 32 static void tci_args_rrrr(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) @@ -434,11 +445,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, TCGReg r0, r1, r2; tcg_target_ulong t0; tcg_target_ulong t1; - tcg_target_ulong t2; TCGCond condition; target_ulong taddr; - uint8_t tmp8; - uint16_t tmp16; + uint8_t pos, len; uint32_t tmp32; uint64_t tmp64; #if TCG_TARGET_REG_BITS == 32 @@ -629,13 +638,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif #if TCG_TARGET_HAS_deposit_i32 case INDEX_op_deposit_i32: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tmp16 = *tb_ptr++; - tmp8 = *tb_ptr++; - tmp32 = (((1 << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp32) | ((t2 << tmp16) & tmp32)); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i32: @@ -791,13 +795,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, #endif #if TCG_TARGET_HAS_deposit_i64 case INDEX_op_deposit_i64: - t0 = *tb_ptr++; - t1 = tci_read_rval(regs, &tb_ptr); - t2 = tci_read_rval(regs, &tb_ptr); - tmp16 = *tb_ptr++; - tmp8 = *tb_ptr++; - tmp64 = (((1ULL << tmp8) - 1) << tmp16); - tci_write_reg(regs, t0, (t1 & ~tmp64) | ((t2 << tmp16) & tmp64)); + tci_args_rrrbb(&tb_ptr, &r0, &r1, &r2, &pos, &len); + regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); break; #endif case INDEX_op_brcond_i64: |