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authorRichard Henderson <rth@twiddle.net>2015-07-24 07:16:00 -0700
committerRichard Henderson <rth@twiddle.net>2015-08-24 11:10:54 -0700
commit609ad70562793937257c89d07bf7c1370b9fc9aa (patch)
treefd10a7febb6cfe6934d301b2b2dc7b675bade774 /tcg/tcg-opc.h
parent870ad1547ac53bc79c21d86cf453b3b20cc660a2 (diff)
tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32
Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/tcg-opc.h')
-rw-r--r--tcg/tcg-opc.h7
1 files changed, 5 insertions, 2 deletions
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index f721a5a007..02bbf30387 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -141,8 +141,11 @@ DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
/* size changing ops */
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
DEF(extu_i32_i64, 1, 1, 0, IMPL64)
-DEF(trunc_shr_i64_i32, 1, 1, 1,
- IMPL(TCG_TARGET_HAS_trunc_shr_i64_i32)
+DEF(extrl_i64_i32, 1, 1, 0,
+ IMPL(TCG_TARGET_HAS_extrl_i64_i32)
+ | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
+DEF(extrh_i64_i32, 1, 1, 0,
+ IMPL(TCG_TARGET_HAS_extrh_i64_i32)
| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)