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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-02-24 07:45:43 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-02-24 07:45:43 +0000
commitf8422f52fd633bb33e83e686e29c158bde4a3623 (patch)
treef892affe73bc030d10171bd97071f8d184b6507b /tcg/tcg-op.h
parentf65fb10982229b15702dc5f1e675cf30a14ca11a (diff)
More helper types, rearrange generic definitions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3988 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/tcg-op.h')
-rw-r--r--tcg/tcg-op.h109
1 files changed, 109 insertions, 0 deletions
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index be504643c3..0126a39cdd 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -192,6 +192,33 @@ static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2)
0, NULL, 2, args);
}
+static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2,
+ TCGv arg3, TCGv arg4)
+{
+ TCGv args[4];
+ args[0] = arg1;
+ args[1] = arg2;
+ args[2] = arg3;
+ args[3] = arg4;
+ tcg_gen_call(&tcg_ctx,
+ tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
+ 0, NULL, 4, args);
+}
+
+static inline void tcg_gen_helper_1_0(void *func, TCGv ret)
+{
+ tcg_gen_call(&tcg_ctx,
+ tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
+ 1, &ret, 0, NULL);
+}
+
+static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1)
+{
+ tcg_gen_call(&tcg_ctx,
+ tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
+ 1, &ret, 1, &arg1);
+}
+
static inline void tcg_gen_helper_1_2(void *func, TCGv ret,
TCGv arg1, TCGv arg2)
{
@@ -203,6 +230,20 @@ static inline void tcg_gen_helper_1_2(void *func, TCGv ret,
1, &ret, 2, args);
}
+static inline void tcg_gen_helper_1_4(void *func, TCGv ret,
+ TCGv arg1, TCGv arg2, TCGv arg3,
+ TCGv arg4)
+{
+ TCGv args[4];
+ args[0] = arg1;
+ args[1] = arg2;
+ args[2] = arg3;
+ args[3] = arg4;
+ tcg_gen_call(&tcg_ctx,
+ tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
+ 1, &ret, 4, args);
+}
+
/* 32 bit ops */
static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
@@ -1222,6 +1263,8 @@ static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
#endif
}
+#define tcg_gen_ld_ptr tcg_gen_ld_i64
+
#else /* TCG_TARGET_REG_BITS == 32 */
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
@@ -1279,4 +1322,70 @@ static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
}
+#define tcg_gen_ld_ptr tcg_gen_ld_i32
+
#endif /* TCG_TARGET_REG_BITS != 32 */
+
+#if TARGET_LONG_BITS == 64
+#define TCG_TYPE_TL TCG_TYPE_I64
+#define tcg_gen_movi_tl tcg_gen_movi_i64
+#define tcg_gen_mov_tl tcg_gen_mov_i64
+#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
+#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
+#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
+#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
+#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
+#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
+#define tcg_gen_ld_tl tcg_gen_ld_i64
+#define tcg_gen_st8_tl tcg_gen_st8_i64
+#define tcg_gen_st16_tl tcg_gen_st16_i64
+#define tcg_gen_st32_tl tcg_gen_st32_i64
+#define tcg_gen_st_tl tcg_gen_st_i64
+#define tcg_gen_add_tl tcg_gen_add_i64
+#define tcg_gen_addi_tl tcg_gen_addi_i64
+#define tcg_gen_sub_tl tcg_gen_sub_i64
+#define tcg_gen_subi_tl tcg_gen_subi_i64
+#define tcg_gen_and_tl tcg_gen_and_i64
+#define tcg_gen_andi_tl tcg_gen_andi_i64
+#define tcg_gen_or_tl tcg_gen_or_i64
+#define tcg_gen_ori_tl tcg_gen_ori_i64
+#define tcg_gen_xor_tl tcg_gen_xor_i64
+#define tcg_gen_xori_tl tcg_gen_xori_i64
+#define tcg_gen_shl_tl tcg_gen_shl_i64
+#define tcg_gen_shli_tl tcg_gen_shli_i64
+#define tcg_gen_shr_tl tcg_gen_shr_i64
+#define tcg_gen_shri_tl tcg_gen_shri_i64
+#define tcg_gen_sar_tl tcg_gen_sar_i64
+#define tcg_gen_sari_tl tcg_gen_sari_i64
+#else
+#define TCG_TYPE_TL TCG_TYPE_I32
+#define tcg_gen_movi_tl tcg_gen_movi_i32
+#define tcg_gen_mov_tl tcg_gen_mov_i32
+#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
+#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
+#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
+#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
+#define tcg_gen_ld32u_tl tcg_gen_ld_i32
+#define tcg_gen_ld32s_tl tcg_gen_ld_i32
+#define tcg_gen_ld_tl tcg_gen_ld_i32
+#define tcg_gen_st8_tl tcg_gen_st8_i32
+#define tcg_gen_st16_tl tcg_gen_st16_i32
+#define tcg_gen_st32_tl tcg_gen_st_i32
+#define tcg_gen_st_tl tcg_gen_st_i32
+#define tcg_gen_add_tl tcg_gen_add_i32
+#define tcg_gen_addi_tl tcg_gen_addi_i32
+#define tcg_gen_sub_tl tcg_gen_sub_i32
+#define tcg_gen_subi_tl tcg_gen_subi_i32
+#define tcg_gen_and_tl tcg_gen_and_i32
+#define tcg_gen_andi_tl tcg_gen_andi_i32
+#define tcg_gen_or_tl tcg_gen_or_i32
+#define tcg_gen_ori_tl tcg_gen_ori_i32
+#define tcg_gen_xor_tl tcg_gen_xor_i32
+#define tcg_gen_xori_tl tcg_gen_xori_i32
+#define tcg_gen_shl_tl tcg_gen_shl_i32
+#define tcg_gen_shli_tl tcg_gen_shli_i32
+#define tcg_gen_shr_tl tcg_gen_shr_i32
+#define tcg_gen_shri_tl tcg_gen_shri_i32
+#define tcg_gen_sar_tl tcg_gen_sar_i32
+#define tcg_gen_sari_tl tcg_gen_sari_i32
+#endif