diff options
| author | Richard Henderson <rth@twiddle.net> | 2012-09-21 10:34:21 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2012-09-21 22:02:16 +0200 |
| commit | 9b9c37c36439ee0452632253dac7a31897f27f70 (patch) | |
| tree | b5c8fa6937fcc7a4d2f75cd64051f66d6bbfc25b /tcg/sparc/tcg-target.h | |
| parent | d5dd696fe3049657c08eb14f40cb74b6e94e79cc (diff) | |
tcg-sparc: Assume v9 cpu always, i.e. force v8plus in 32-bit mode.
Current code doesn't actually work in 32-bit mode at all. Since
no one really noticed, drop the complication of v7 and v8 cpus.
Eliminate the --sparc_cpu configure option and standardize macro
testing on TCG_TARGET_REG_BITS / HOST_LONG_BITS
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/sparc/tcg-target.h')
| -rw-r--r-- | tcg/sparc/tcg-target.h | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index d76257403d..adca1d2200 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -67,7 +67,8 @@ typedef enum { /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_I6 -#ifdef __arch64__ + +#if TCG_TARGET_REG_BITS == 64 // Reserve space for AREG0 #define TCG_TARGET_STACK_MINFRAME (176 + 4 * (int)sizeof(long) + \ TCG_STATIC_CALL_ARGS_SIZE) @@ -81,7 +82,7 @@ typedef enum { #define TCG_TARGET_STACK_ALIGN 8 #endif -#ifdef __arch64__ +#if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_EXTEND_ARGS 1 #endif @@ -129,7 +130,7 @@ typedef enum { #ifdef CONFIG_SOLARIS #define TCG_AREG0 TCG_REG_G2 -#elif defined(__sparc_v9__) +#elif HOST_LONG_BITS == 64 #define TCG_AREG0 TCG_REG_G5 #else #define TCG_AREG0 TCG_REG_G6 |