diff options
| author | Richard Henderson <rth@twiddle.net> | 2010-02-16 13:55:15 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-02-20 08:31:50 +0000 |
| commit | 4b5a85c175768faf302cf8349d8613dbc1ac5f54 (patch) | |
| tree | 55609f1b9a533dac95824d37d5d19565299548a1 /tcg/sparc/tcg-target.c | |
| parent | 4fc8d6711aff7a9c11e402c3d77b481609f9f486 (diff) | |
tcg-sparc: Implement neg.
The fallback implementation of "ret = 0 - arg1" isn't ideal,
first because of the extra tcg op to load the zero, and second
because we fail to handle zero as %g0 for arg1 of the sub.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'tcg/sparc/tcg-target.c')
| -rw-r--r-- | tcg/sparc/tcg-target.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 5b4347ad89..f5cf95d51b 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1234,6 +1234,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, c = ARITH_UMUL; goto gen_arith; + OP_32_64(neg): + c = ARITH_SUB; + goto gen_arith1; + case INDEX_op_div_i32: tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 0); break; @@ -1392,6 +1396,10 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, tcg_out_arithc(s, args[0], args[1], args[2], const_args[2], c); break; + gen_arith1: + tcg_out_arithc(s, args[0], TCG_REG_G0, args[1], const_args[1], c); + break; + default: fprintf(stderr, "unknown opcode 0x%x\n", opc); tcg_abort(); @@ -1431,6 +1439,8 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_shr_i32, { "r", "r", "rJ" } }, { INDEX_op_sar_i32, { "r", "r", "rJ" } }, + { INDEX_op_neg_i32, { "r", "rJ" } }, + { INDEX_op_brcond_i32, { "r", "rJ" } }, { INDEX_op_setcond_i32, { "r", "r", "rJ" } }, @@ -1484,6 +1494,9 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_shl_i64, { "r", "r", "rJ" } }, { INDEX_op_shr_i64, { "r", "r", "rJ" } }, { INDEX_op_sar_i64, { "r", "r", "rJ" } }, + + { INDEX_op_neg_i64, { "r", "rJ" } }, + { INDEX_op_ext32s_i64, { "r", "ri" } }, { INDEX_op_ext32u_i64, { "r", "ri" } }, |