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authorRichard Henderson <richard.henderson@linaro.org>2017-09-11 12:44:30 -0700
committerRichard Henderson <richard.henderson@linaro.org>2017-09-17 06:52:19 -0700
commitf46934df662182097dce07d57ec00f37e4d2abf1 (patch)
tree17cb6113bf3f6e248669ba4aa813fa8eb222b883 /tcg/s390
parent07ddf036fa66bca279590c09fe1c46bcdcc5bcff (diff)
tcg: Remove tcg_regset_set32
It's not even clear what the interface REG and VAL32 were supposed to mean. All uses had REG = 0 and VAL32 was the bitset assigned to the destination. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/s390')
-rw-r--r--tcg/s390/tcg-target.inc.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 01baa33673..38a7cdab75 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -402,14 +402,14 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) {
case 'r': /* all registers */
ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xffff);
+ ct->u.regs = 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, 0xffff);
- tcg_regset_reset_reg (ct->u.regs, TCG_REG_R2);
- tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
- tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
+ ct->u.regs = 0xffff;
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
+ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG;
@@ -2519,8 +2519,8 @@ static void tcg_target_init(TCGContext *s)
{
query_s390_facilities();
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff);
+ tcg_target_available_regs[TCG_TYPE_I32] = 0xffff;
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffff;
tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0);