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authorSergey Sorokin <afarallax@yandex.ru>2016-06-23 21:16:46 +0300
committerRichard Henderson <rth@twiddle.net>2016-07-05 20:50:13 -0700
commit1f00b27f17518a1bcb4cedca49eaec96a4d560bd (patch)
tree90abe3fc60c60ce9ff0aa5c46a87c5589ff55229 /tcg/s390/tcg-target.inc.c
parent59d7c14eeff8d2ad7f61aed86ce5a176113bc153 (diff)
tcg: Improve the alignment check infrastructure
Some architectures (e.g. ARMv8) need the address which is aligned to a size more than the size of the memory access. To support such check it's enough the current costless alignment check implementation in QEMU, but we need to support an alignment size specifying. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-Id: <1466705806-679898-1-git-send-email-afarallax@yandex.ru> Signed-off-by: Richard Henderson <rth@twiddle.net> [rth: Assert in tcg_canonicalize_memop. Leave get_alignment_bits available for, though unused by, user-mode. Retain logging difference based on ALIGNED_ONLY.]
Diffstat (limited to 'tcg/s390/tcg-target.inc.c')
-rw-r--r--tcg/s390/tcg-target.inc.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 314c1834aa..5a7495b063 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1505,18 +1505,19 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
static TCGReg tcg_out_tlb_read(TCGContext* s, TCGReg addr_reg, TCGMemOp opc,
int mem_index, bool is_ld)
{
- int s_mask = (1 << (opc & MO_SIZE)) - 1;
+ int a_bits = get_alignment_bits(opc);
int ofs, a_off;
uint64_t tlb_mask;
/* For aligned accesses, we check the first byte and include the alignment
bits within the address. For unaligned access, we check that we don't
cross pages using the address of the last byte of the access. */
- if ((opc & MO_AMASK) == MO_ALIGN || s_mask == 0) {
+ if (a_bits >= 0) {
+ /* A byte access or an alignment check required */
a_off = 0;
- tlb_mask = TARGET_PAGE_MASK | s_mask;
+ tlb_mask = TARGET_PAGE_MASK | ((1 << a_bits) - 1);
} else {
- a_off = s_mask;
+ a_off = (1 << (opc & MO_SIZE)) - 1;
tlb_mask = TARGET_PAGE_MASK;
}