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author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-30 08:57:20 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2020-10-08 05:57:32 -0500 |
commit | e2e7168a214b0ed98dc357bba96816486a289762 (patch) | |
tree | da936e20dd164e5997a49cca286266d85ad54cd8 /tcg/riscv | |
parent | 6eeea6725a70e6fcb5abba0764496bdab07ddfb3 (diff) |
tcg: Adjust simd_desc size encoding
With larger vector sizes, it turns out oprsz == maxsz, and we only
need to represent mismatch for oprsz <= 32. We do, however, need
to represent larger oprsz and do so without reducing SIMD_DATA_BITS.
Reduce the size of the oprsz field and increase the maxsz field.
Steal the oprsz value of 24 to indicate equality with maxsz.
Tested-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
0 files changed, 0 insertions, 0 deletions