diff options
| author | Bin Meng <bmeng@tinylab.org> | 2022-12-11 11:08:29 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
| commit | bc92f261519d5c77c70cf2ebcf0a3b9a414d82d0 (patch) | |
| tree | 09e863bfecd790203d782813258b0afee4ff1688 /tcg/riscv | |
| parent | a984e2b32f6da127f3b9ee1a72bde9b68effaa80 (diff) | |
hw/intc: sifive_plic: Fix the pending register range check
The pending register upper limit is currently set to
plic->num_sources >> 3, which is wrong, e.g.: considering
plic->num_sources is 7, the upper limit becomes 0 which fails
the range check if reading the pending register at pending_base.
Fixes: 1e24429e40df ("SiFive RISC-V PLIC Block")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221211030829.802437-16-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'tcg/riscv')
0 files changed, 0 insertions, 0 deletions