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| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 14:49:59 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:21:19 +0100 |
| commit | 753e42eada5c790bb3727c262f2e368e81cc788f (patch) | |
| tree | 854969ea72b1ed34b29709139bafc6a4b9cc656d /tcg/riscv | |
| parent | d0e66c897f2cdfb0807b76567a17d7811487fac3 (diff) | |
tcg: Split out tcg_out_ext16s
We will need a backend interface for performing 16-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/riscv')
| -rw-r--r-- | tcg/riscv/tcg-target.c.inc | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index d9b08014ce..12ee7b29af 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -591,7 +591,7 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); } -static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) { tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); @@ -1607,11 +1607,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_ext32u(s, a0, a1); break; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - tcg_out_ext16s(s, a0, a1); - break; - case INDEX_op_ext32s_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_ext_i32_i64: @@ -1645,6 +1640,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } |