diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-04-04 12:47:22 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-04-15 20:09:55 +0200 |
| commit | 39dc85b98561ea3de2b029f43a3a2db95c57afa3 (patch) | |
| tree | 3787ec62097954e4e148c98968c1b0298683d3ef /tcg/ppc64 | |
| parent | 6645c147db4bb84b1b24c49be9398be22902923b (diff) | |
tcg-ppc64: Handle deposit of zero
The TCG optimizer does great work when inserting constants, being able
to fold the open-coded deposit expansion to just an AND or an OR. Avoid
a bit the regression caused by having the deposit opcode by expanding
deposit of zero as an AND.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/ppc64')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 0f335837b6..0fcf2b5daa 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -1928,12 +1928,22 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc, const TCGArg *args, break; case INDEX_op_deposit_i32: - tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], - 32 - args[3] - args[4], 31 - args[3]); + if (const_args[2]) { + uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi32(s, args[0], args[0], ~mask); + } else { + tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], + 32 - args[3] - args[4], 31 - args[3]); + } break; case INDEX_op_deposit_i64: - tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], - 64 - args[3] - args[4]); + if (const_args[2]) { + uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; + tcg_out_andi64(s, args[0], args[0], ~mask); + } else { + tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], + 64 - args[3] - args[4]); + } break; case INDEX_op_movcond_i32: @@ -2136,8 +2146,8 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_bswap32_i64, { "r", "r" } }, { INDEX_op_bswap64_i64, { "r", "r" } }, - { INDEX_op_deposit_i32, { "r", "0", "r" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, + { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, + { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, { INDEX_op_add2_i64, { "r", "r", "r", "rI", "r", "rZM" } }, { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } }, |