diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-19 15:13:22 +0200 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-05-30 09:51:11 -0700 |
| commit | 526cd4ec01fed36a2a6937fe54eb80d6d7f4c4e4 (patch) | |
| tree | 31e984f6ab8b2408435b9d6406bfe4edbed15331 /tcg/ppc/tcg-target.h | |
| parent | 929124ec0bdbfac11ae27378976e5799ca0d54cc (diff) | |
tcg/ppc: Support 128-bit load/store
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required.
Note that these instructions do not require 16-byte alignment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/ppc/tcg-target.h')
| -rw-r--r-- | tcg/ppc/tcg-target.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 0914380bd7..204b70f86a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -149,7 +149,8 @@ extern bool have_vsx; #define TCG_TARGET_HAS_mulsh_i64 1 #endif -#define TCG_TARGET_HAS_qemu_ldst_i128 0 +#define TCG_TARGET_HAS_qemu_ldst_i128 \ + (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) /* * While technically Altivec could support V64, it has no 64-bit store |