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authormalc <av1474@comtv.ru>2010-04-05 16:08:47 +0400
committermalc <av1474@comtv.ru>2010-04-05 16:09:05 +0400
commitaa77bebd989469a973cc1dfb4d582d4655a4adde (patch)
tree3ce581ad29ac781713627be7c16395ea78d89b79 /tcg/ppc/tcg-target.c
parent355b194369d02df7a97d554eef2a9cffe98d736f (diff)
tcg/ppc: Implement eqv, nand and nor
Signed-off-by: malc <av1474@comtv.ru>
Diffstat (limited to 'tcg/ppc/tcg-target.c')
-rw-r--r--tcg/ppc/tcg-target.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 609035a076..a40883bde0 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -369,6 +369,8 @@ static int tcg_target_const_match(tcg_target_long val,
#define NOR XO31(124)
#define ANDC XO31( 60)
#define ORC XO31(412)
+#define EQV XO31(284)
+#define NAND XO31(476)
#define LBZX XO31( 87)
#define LHZX XO31(279)
@@ -1475,6 +1477,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
case INDEX_op_orc_i32:
tcg_out32 (s, ORC | SAB (args[1], args[0], args[2]));
break;
+ case INDEX_op_eqv_i32:
+ tcg_out32 (s, EQV | SAB (args[1], args[0], args[2]));
+ break;
+ case INDEX_op_nand_i32:
+ tcg_out32 (s, NAND | SAB (args[1], args[0], args[2]));
+ break;
+ case INDEX_op_nor_i32:
+ tcg_out32 (s, NOR | SAB (args[1], args[0], args[2]));
+ break;
case INDEX_op_mul_i32:
if (const_args[2]) {
@@ -1758,6 +1769,9 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_andc_i32, { "r", "r", "r" } },
{ INDEX_op_orc_i32, { "r", "r", "r" } },
+ { INDEX_op_eqv_i32, { "r", "r", "r" } },
+ { INDEX_op_nand_i32, { "r", "r", "r" } },
+ { INDEX_op_nor_i32, { "r", "r", "r" } },
{ INDEX_op_setcond_i32, { "r", "r", "ri" } },
{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },