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authorRichard Henderson <richard.henderson@linaro.org>2023-04-19 15:13:22 +0200
committerRichard Henderson <richard.henderson@linaro.org>2023-05-30 09:51:11 -0700
commit526cd4ec01fed36a2a6937fe54eb80d6d7f4c4e4 (patch)
tree31e984f6ab8b2408435b9d6406bfe4edbed15331 /tcg/ppc/tcg-target-con-str.h
parent929124ec0bdbfac11ae27378976e5799ca0d54cc (diff)
tcg/ppc: Support 128-bit load/store
Use LQ/STQ with ISA v2.07, and 16-byte atomicity is required. Note that these instructions do not require 16-byte alignment. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/ppc/tcg-target-con-str.h')
-rw-r--r--tcg/ppc/tcg-target-con-str.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/tcg/ppc/tcg-target-con-str.h b/tcg/ppc/tcg-target-con-str.h
index 094613cbcb..20846901de 100644
--- a/tcg/ppc/tcg-target-con-str.h
+++ b/tcg/ppc/tcg-target-con-str.h
@@ -9,6 +9,7 @@
* REGS(letter, register_mask)
*/
REGS('r', ALL_GENERAL_REGS)
+REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */
REGS('v', ALL_VECTOR_REGS)
/*