diff options
| author | Richard Henderson <rth@twiddle.net> | 2016-10-14 15:50:25 -0500 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:03:59 -0800 |
| commit | befbb3ced5869003ee2e806c4f36e306918d2374 (patch) | |
| tree | d85e17ac1cedf5f7ae5d3b4f932b887957d086b8 /tcg/mips | |
| parent | 78fdbfb94616f0391834d2eccabd16ea29e37da5 (diff) | |
tcg/mips: Implement field extraction opcodes
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.h | 4 | ||||
| -rw-r--r-- | tcg/mips/tcg-target.inc.c | 9 |
2 files changed, 12 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index fcc2986cd5..92d203aca8 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -158,7 +158,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions -#define TCG_TARGET_HAS_extract_i32 0 +#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_sextract_i32 0 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions @@ -170,6 +170,8 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions +#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions +#define TCG_TARGET_HAS_sextract_i64 0 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 5b2fe988de..24c49497a9 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2051,6 +2051,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, args[3] + args[4] - 1, args[3]); break; + case INDEX_op_extract_i32: + tcg_out_opc_bf(s, OPC_EXT, a0, a1, a2 + args[3] - 1, a2); + break; + case INDEX_op_extract_i64: + tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, + a2 + args[3] - 1, a2); + break; case INDEX_op_brcond_i32: case INDEX_op_brcond_i64: @@ -2155,6 +2162,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_ext16s_i32, { "r", "rZ" } }, { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, + { INDEX_op_extract_i32, { "r", "r" } }, { INDEX_op_brcond_i32, { "rZ", "rZ" } }, #if use_mips32r6_instructions @@ -2224,6 +2232,7 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_extrh_i64_i32, { "r", "rZ" } }, { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, + { INDEX_op_extract_i64, { "r", "r" } }, { INDEX_op_brcond_i64, { "rZ", "rZ" } }, #if use_mips32r6_instructions |