aboutsummaryrefslogtreecommitdiff
path: root/tcg/mips
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2023-04-05 13:26:51 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-04-23 08:18:04 +0100
commitd0e66c897f2cdfb0807b76567a17d7811487fac3 (patch)
tree32008e904c4781188f591a9314af234095c5dfcd /tcg/mips
parent678155b2c50aa3bf37abef6bfe914bf58f49bec2 (diff)
tcg: Split out tcg_out_ext8u
We will need a backend interface for performing 8-bit zero-extend. Use it in tcg_reg_alloc_op in the meantime. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips')
-rw-r--r--tcg/mips/tcg-target.c.inc9
1 files changed, 8 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 8fc9d02bd5..5a712e3da5 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -558,6 +558,11 @@ static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs);
}
+static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs)
+{
+ tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff);
+}
+
static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
tcg_target_long imm)
{
@@ -1099,7 +1104,7 @@ static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg)
if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) {
tmp = tcg_target_call_iarg_regs[i];
}
- tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff);
+ tcg_out_ext8u(s, tmp, arg);
return tcg_out_call_iarg_reg(s, i, tmp);
}
@@ -2423,6 +2428,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */
case INDEX_op_ext8s_i64:
+ case INDEX_op_ext8u_i32:
+ case INDEX_op_ext8u_i64:
default:
g_assert_not_reached();
}