diff options
| author | Richard Henderson <rth@twiddle.net> | 2014-04-15 22:41:46 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2014-05-24 08:46:58 -0700 |
| commit | 1db1c4d7d91843dd6a7dab93946e01bc19e8ba38 (patch) | |
| tree | 022850bbcf7fcdd8f6ba2adb00b307c31d6f4252 /tcg/mips/tcg-target.c | |
| parent | 9a2f0bfe32bc61d079eb2d763dae1616697f85c4 (diff) | |
tcg-mips: Improve setcond eq/ne vs zeros
The original code results in one too many insns per zero
present in the input. And since comparing 64-bit numbers
vs zero is common...
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/mips/tcg-target.c')
| -rw-r--r-- | tcg/mips/tcg-target.c | 40 |
1 files changed, 36 insertions, 4 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 1429ec715e..ccf262b217 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -701,6 +701,40 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, tcg_out_nop(s); } +static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, + TCGReg al, TCGReg ah, + TCGReg bl, TCGReg bh) +{ + /* Merge highpart comparison into AH. */ + if (bh != 0) { + if (ah != 0) { + tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); + ah = tmp0; + } else { + ah = bh; + } + } + /* Merge lowpart comparison into AL. */ + if (bl != 0) { + if (al != 0) { + tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); + al = tmp1; + } else { + al = bl; + } + } + /* Merge high and low part comparisons into AL. */ + if (ah != 0) { + if (al != 0) { + tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); + al = tmp0; + } else { + al = ah; + } + } + return al; +} + static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) { @@ -716,10 +750,8 @@ static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, switch (cond) { case TCG_COND_EQ: case TCG_COND_NE: - tcg_out_setcond(s, cond, tmp0, ah, bh); - tcg_out_setcond(s, cond, ret, al, bl); - tcg_out_opc_reg(s, (cond == TCG_COND_EQ ? OPC_AND : OPC_OR), - ret, ret, tmp0); + tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); + tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); break; default: |