diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 18:07:05 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:23:59 +0100 |
| commit | 9ecf5f61b8f468f17483f325f565802c645983a5 (patch) | |
| tree | 1e7d5ebf403a130c229e5c13d903da018069aac9 /tcg/mips/tcg-target.c.inc | |
| parent | 52bf3398c3a2f51d3eaf8fd30dafcdc0cc7fc571 (diff) | |
tcg: Split out tcg_out_ext32u
We will need a backend interface for performing 32-bit zero-extend.
Use it in tcg_reg_alloc_op in the meantime.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips/tcg-target.c.inc')
| -rw-r--r-- | tcg/mips/tcg-target.c.inc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index c57ccb6b3d..fe90547c43 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -663,6 +663,7 @@ static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) { + tcg_debug_assert(TCG_TARGET_REG_BITS == 64); if (use_mips32r2_instructions) { tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); } else { @@ -2297,7 +2298,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_extrl_i64_i32: tcg_out_ext32s(s, a0, a1); break; - case INDEX_op_ext32u_i64: case INDEX_op_extu_i32_i64: tcg_out_ext32u(s, a0, a1); break; @@ -2446,6 +2446,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16s_i32: case INDEX_op_ext16s_i64: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } |