diff options
| author | Jiajie Chen <c@jia.je> | 2023-09-08 10:21:19 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-09-15 05:26:51 -0700 |
| commit | c8b859b45e25000a427fbb4aa8ebcc55c7777503 (patch) | |
| tree | 548d3f685229d4ae0c937c984d6e204935ef1045 /tcg/loongarch64 | |
| parent | 94304d7b3dead74e87fdb557e909b57bf0f468da (diff) | |
tcg/loongarch64: Lower bitsel_vec to vbitsel
Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230908022302.180442-13-c@jia.je>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/loongarch64')
| -rw-r--r-- | tcg/loongarch64/tcg-target-con-set.h | 1 | ||||
| -rw-r--r-- | tcg/loongarch64/tcg-target.c.inc | 11 | ||||
| -rw-r--r-- | tcg/loongarch64/tcg-target.h | 2 |
3 files changed, 12 insertions, 2 deletions
diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index 3f530ad4d8..914572d21b 100644 --- a/tcg/loongarch64/tcg-target-con-set.h +++ b/tcg/loongarch64/tcg-target-con-set.h @@ -35,4 +35,5 @@ C_O1_I2(r, rZ, rZ) C_O1_I2(w, w, w) C_O1_I2(w, w, wM) C_O1_I2(w, w, wA) +C_O1_I3(w, w, w, w) C_O1_I4(r, rZ, rJ, rZ, rZ) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 6958fd219c..a33ec594ee 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1676,7 +1676,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, const int const_args[TCG_MAX_OP_ARGS]) { TCGType type = vecl + TCG_TYPE_V64; - TCGArg a0, a1, a2; + TCGArg a0, a1, a2, a3; TCGReg temp = TCG_REG_TMP0; TCGReg temp_vec = TCG_VEC_TMP0; @@ -1738,6 +1738,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, a0 = args[0]; a1 = args[1]; a2 = args[2]; + a3 = args[3]; /* Currently only supports V128 */ tcg_debug_assert(type == TCG_TYPE_V128); @@ -1871,6 +1872,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_sarv_vec: tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2)); break; + case INDEX_op_bitsel_vec: + /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ + tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); + break; case INDEX_op_dupm_vec: tcg_out_dupm_vec(s, type, vece, a0, a1, a2); break; @@ -1909,6 +1914,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shlv_vec: case INDEX_op_shrv_vec: case INDEX_op_sarv_vec: + case INDEX_op_bitsel_vec: return 1; default: return 0; @@ -2101,6 +2107,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_neg_vec: return C_O1_I1(w, w); + case INDEX_op_bitsel_vec: + return C_O1_I3(w, w, w, w); + default: g_assert_not_reached(); } diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 7e9fb61c47..bc56939a57 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -194,7 +194,7 @@ extern bool use_lsx_instructions; #define TCG_TARGET_HAS_rotv_vec 0 #define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 1 -#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 1 #define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_DEFAULT_MO (0) |