diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-10 18:30:05 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-01-12 00:06:07 +0100 |
| commit | 56779034530944eb6171d843f652f3fba710ed30 (patch) | |
| tree | bdb4eb8143f70a010b216e2c9921f7bb84fac55b /tcg/ia64/tcg-target.c | |
| parent | dace20dcc98f90a931e88aa641f5633cdcf30c30 (diff) | |
tcg arm/mips/ia64: add a comment about retranslation and caches
Add a comment about cache coherency and retranslation, so that people
developping new targets based on existing ones are warned of the issue.
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/ia64/tcg-target.c')
| -rw-r--r-- | tcg/ia64/tcg-target.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c index e2e44f7d76..8dac7f72fd 100644 --- a/tcg/ia64/tcg-target.c +++ b/tcg/ia64/tcg-target.c @@ -871,6 +871,9 @@ static void tcg_out_br(TCGContext *s, int label_index) { TCGLabel *l = &s->labels[label_index]; + /* We pay attention here to not modify the branch target by reading + the existing value and using it again. This ensure that caches and + memory are kept coherent during retranslation. */ tcg_out_bundle(s, mmB, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), |