diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2020-12-09 13:58:39 -0600 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-01-07 05:09:06 -1000 |
| commit | 07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1 (patch) | |
| tree | a22f2b213b2cb96c8e0e30c69bca9edb00b678bc /tcg/i386/tcg-target.h | |
| parent | d2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5 (diff) | |
tcg: Introduce INDEX_op_qemu_st8_i32
Enable this on i386 to restrict the set of input registers
for an 8-bit store, as required by the architecture. This
removes the last use of scratch registers for user-only mode.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/i386/tcg-target.h')
| -rw-r--r-- | tcg/i386/tcg-target.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b1ada9777a..f3836a4d0c 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -172,6 +172,9 @@ extern bool have_movbe; #define TCG_TARGET_HAS_muls2_i64 1 #define TCG_TARGET_HAS_muluh_i64 0 #define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_qemu_st8_i32 0 +#else +#define TCG_TARGET_HAS_qemu_st8_i32 1 #endif /* We do not support older SSE systems, only beginning with AVX1. */ |