diff options
author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-23 18:51:15 +0000 |
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committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-05-23 18:51:15 +0000 |
commit | 91a3c1b00d040f92f4bdca5825e5d2205d417c2f (patch) | |
tree | b0d15c1609f4cc71b3c919bb7bc0062e7b369b6f /tcg/arm | |
parent | e936243acad7a657d26560d16a1cb2a505936c2d (diff) |
Comment non-obvious calculation. Don't clobber r3 in qemu_st64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'tcg/arm')
-rw-r--r-- | tcg/arm/tcg-target.c | 39 |
1 files changed, 33 insertions, 6 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index 53bd366c60..6c8717ee32 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -854,12 +854,27 @@ static inline void tcg_out_qemu_ld(TCGContext *s, int cond, s_bits = opc & 3; # ifdef USE_TLB + /* Should generate something like the following: + * ror r8, addr_reg, #TARGET_PAGE_BITS + * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 + * add r0, T0, r0 lsl #CPU_TLB_ENTRY_BITS + */ +# if CPU_TLB_BITS > 8 +# error +# endif tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 8, 0, addr_reg, SHIFT_IMM_ROR(TARGET_PAGE_BITS)); tcg_out_dat_imm(s, COND_AL, ARITH_AND, 0, 8, CPU_TLB_SIZE - 1); tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); + /* In the + * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))] + * below, the offset is likely to exceed 12 bits if mem_index != 0 and + * not exceed otherwise, so use an + * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table) + * before. + */ # define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) if (mem_index) tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0, @@ -1025,12 +1040,24 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond, s_bits = opc & 3; # ifdef USE_TLB + /* Should generate something like the following: + * ror r8, addr_reg, #TARGET_PAGE_BITS + * and r0, r8, #(CPU_TLB_SIZE - 1) @ Assumption: CPU_TLB_BITS <= 8 + * add r0, T0, r0 lsl #CPU_TLB_ENTRY_BITS + */ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 8, 0, addr_reg, SHIFT_IMM_ROR(TARGET_PAGE_BITS)); tcg_out_dat_imm(s, COND_AL, ARITH_AND, 0, 8, CPU_TLB_SIZE - 1); tcg_out_dat_reg(s, COND_AL, ARITH_ADD, 0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); + /* In the + * ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))] + * below, the offset is likely to exceed 12 bits if mem_index != 0 and + * not exceed otherwise, so use an + * add r0, r0, #(mem_index * sizeof *CPUState.tlb_table) + * before. + */ if (mem_index) tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0, (mem_index << (TLB_SHIFT & 1)) | @@ -1084,10 +1111,6 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond, tcg_out_b(s, COND_EQ, 8); # endif -# ifdef SAVE_LR - tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0)); -# endif - /* TODO: move this code to where the constants pool will be */ if (addr_reg) tcg_out_dat_reg(s, cond, ARITH_MOV, @@ -1144,8 +1167,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond, tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index); break; case 3: - tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index); - tcg_out32(s, (cond << 28) | 0x052d3010); /* str r3, [sp, #-0x10]! */ + tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index); + tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */ if (data_reg != 2) tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, data_reg, SHIFT_IMM_LSL(0)); @@ -1156,6 +1179,10 @@ static inline void tcg_out_qemu_st(TCGContext *s, int cond, } # endif +# ifdef SAVE_LR + tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0)); +# endif + tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] - (tcg_target_long) s->code_ptr); |