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authorRichard Henderson <rth@twiddle.net>2013-06-07 07:26:20 -0700
committerRichard Henderson <rth@twiddle.net>2013-11-30 07:45:14 +1300
commit41d9ea80ac8455845494c889fe6ac447b39a7d64 (patch)
tree3c8988e5a3d1bbfbf7fedb35269d958c3adb3ab1 /tcg/arm
parentcd629de1cf013e9654c6f0b92b2329f04dfaf880 (diff)
tcg-arm: Use qemu_getauxval
Allow host detection on linux systems without glibc 2.16 or later. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/arm')
-rw-r--r--tcg/arm/tcg-target.c14
1 files changed, 5 insertions, 9 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index e93a4a237b..82658a170c 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
+#include "elf.h"
#include "tcg-be-ldst.h"
/* The __ARM_ARCH define is provided by gcc 4.8. Construct it otherwise. */
@@ -58,9 +59,6 @@ static int arm_arch = __ARM_ARCH;
#ifndef use_idiv_instructions
bool use_idiv_instructions;
#endif
-#ifdef CONFIG_GETAUXVAL
-# include <sys/auxv.h>
-#endif
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@@ -2036,22 +2034,20 @@ static const TCGTargetOpDef arm_op_defs[] = {
static void tcg_target_init(TCGContext *s)
{
-#if defined(CONFIG_GETAUXVAL)
/* Only probe for the platform and capabilities if we havn't already
determined maximum values at compile time. */
-# if !defined(use_idiv_instructions)
+#ifndef use_idiv_instructions
{
- unsigned long hwcap = getauxval(AT_HWCAP);
+ unsigned long hwcap = qemu_getauxval(AT_HWCAP);
use_idiv_instructions = (hwcap & HWCAP_ARM_IDIVA) != 0;
}
-# endif
+#endif
if (__ARM_ARCH < 7) {
- const char *pl = (const char *)getauxval(AT_PLATFORM);
+ const char *pl = (const char *)qemu_getauxval(AT_PLATFORM);
if (pl != NULL && pl[0] == 'v' && pl[1] >= '4' && pl[1] <= '9') {
arm_arch = pl[1] - '0';
}
}
-#endif /* GETAUXVAL */
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff);
tcg_regset_set32(tcg_target_call_clobber_regs, 0,