diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-03-18 15:32:44 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-05-13 14:44:03 -0700 |
| commit | e7632cfa8b76cdbbc1c76e8737338ef5844e7d60 (patch) | |
| tree | 3640a25371b80c87e70b37688d529eeb0dd70282 /tcg/aarch64 | |
| parent | 240c08d0998f402c325fce489de0d14831048128 (diff) | |
tcg: Promote tcg_out_{dup,dupi}_vec to backend interface
The i386 backend already has these functions, and the aarch64 backend
could easily split out one. Nothing is done with these functions yet,
but this will aid register allocation of INDEX_op_dup_vec in a later patch.
Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/aarch64')
| -rw-r--r-- | tcg/aarch64/tcg-target.inc.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index ee89734318..e443b5df23 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -799,7 +799,7 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, } static void tcg_out_dupi_vec(TCGContext *s, TCGType type, - TCGReg rd, uint64_t v64) + TCGReg rd, tcg_target_long v64) { int op, cmode, imm8; @@ -814,6 +814,14 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, } } +static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, + TCGReg rd, TCGReg rs) +{ + int is_q = type - TCG_TYPE_V64; + tcg_out_insn(s, 3605, DUP, is_q, rd, rs, 1 << vece, 0); + return true; +} + static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { @@ -2201,7 +2209,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; case INDEX_op_dup_vec: - tcg_out_insn(s, 3605, DUP, is_q, a0, a1, 1 << vece, 0); + tcg_out_dup_vec(s, type, vece, a0, a1); break; case INDEX_op_shli_vec: tcg_out_insn(s, 3614, SHL, is_q, a0, a1, a2 + (8 << vece)); |