diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2018-12-18 07:14:23 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-01-28 07:03:34 -0800 |
| commit | d32648d445c534cea7e2ad7ed8608208aa8831c1 (patch) | |
| tree | 44ab8d496e6811542a660cd4bb2e4fb0bf050144 /tcg/aarch64/tcg-target.inc.c | |
| parent | bc37faf4cb2baa77c44298c01558970b88d32808 (diff) | |
tcg/aarch64: Implement vector saturating arithmetic
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/aarch64/tcg-target.inc.c')
| -rw-r--r-- | tcg/aarch64/tcg-target.inc.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 0562e0aa40..b2b011f130 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -528,6 +528,10 @@ typedef enum { I3616_CMHI = 0x2e203400, I3616_CMHS = 0x2e203c00, I3616_CMEQ = 0x2e208c00, + I3616_SQADD = 0x0e200c00, + I3616_SQSUB = 0x0e202c00, + I3616_UQADD = 0x2e200c00, + I3616_UQSUB = 0x2e202c00, /* AdvSIMD two-reg misc. */ I3617_CMGT0 = 0x0e208800, @@ -2137,6 +2141,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_orc_vec: tcg_out_insn(s, 3616, ORN, is_q, 0, a0, a1, a2); break; + case INDEX_op_ssadd_vec: + tcg_out_insn(s, 3616, SQADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_sssub_vec: + tcg_out_insn(s, 3616, SQSUB, is_q, vece, a0, a1, a2); + break; + case INDEX_op_usadd_vec: + tcg_out_insn(s, 3616, UQADD, is_q, vece, a0, a1, a2); + break; + case INDEX_op_ussub_vec: + tcg_out_insn(s, 3616, UQSUB, is_q, vece, a0, a1, a2); + break; case INDEX_op_not_vec: tcg_out_insn(s, 3617, NOT, is_q, 0, a0, a1); break; @@ -2207,6 +2223,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return 1; case INDEX_op_mul_vec: return vece < MO_64; @@ -2386,6 +2406,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_xor_vec: case INDEX_op_andc_vec: case INDEX_op_orc_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return &w_w_w; case INDEX_op_not_vec: case INDEX_op_neg_vec: |