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| author | Max Filippov <jcmvbkbc@gmail.com> | 2011-11-26 15:48:41 +0400 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-16 19:19:03 -0800 |
| commit | 3a3c9dc4ca2eaa612cbd5d4c85d674b15eadfb02 (patch) | |
| tree | d64a088bd5188f6b19fe1fcd341283140f5fcc0e /tcg/aarch64/tcg-target.h | |
| parent | 8b912ff033cbc2e58476dfdc00fa2b8529c9eb96 (diff) | |
target-xtensa: implement RER/WER instructions
RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tcg/aarch64/tcg-target.h')
0 files changed, 0 insertions, 0 deletions