diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 18:07:05 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:23:59 +0100 |
| commit | 9ecf5f61b8f468f17483f325f565802c645983a5 (patch) | |
| tree | 1e7d5ebf403a130c229e5c13d903da018069aac9 /tcg/aarch64/tcg-target.c.inc | |
| parent | 52bf3398c3a2f51d3eaf8fd30dafcdc0cc7fc571 (diff) | |
tcg: Split out tcg_out_ext32u
We will need a backend interface for performing 32-bit zero-extend.
Use it in tcg_reg_alloc_op in the meantime.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/aarch64/tcg-target.c.inc')
| -rw-r--r-- | tcg/aarch64/tcg-target.c.inc | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index d7964734c3..bca5f03dfb 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1452,6 +1452,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rn) tcg_out_uxt(s, MO_16, rd, rn); } +static void tcg_out_ext32u(TCGContext *s, TCGReg rd, TCGReg rn) +{ + tcg_out_movr(s, TCG_TYPE_I32, rd, rn); +} + static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd, TCGReg rn, int64_t aimm) { @@ -2259,8 +2264,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_sxt(s, TCG_TYPE_I64, MO_32, a0, a1); break; case INDEX_op_extu_i32_i64: - case INDEX_op_ext32u_i64: - tcg_out_movr(s, TCG_TYPE_I32, a0, a1); + tcg_out_ext32u(s, a0, a1); break; case INDEX_op_deposit_i64: @@ -2327,6 +2331,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext16u_i64: case INDEX_op_ext16u_i32: case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: default: g_assert_not_reached(); } |