diff options
author | Richard Henderson <rth@twiddle.net> | 2016-10-15 13:37:19 -0500 |
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committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:06:10 -0800 |
commit | 7b4d326f479fd94869eb4b81715691ce68a6b110 (patch) | |
tree | 49011786ad36405311d5d7d491175986cca324ba /target | |
parent | 6eebb7a438236fcf3fdadb013921ac597aaea911 (diff) |
target-ppc: Use the new deposit and extract ops
Use the new primitives for RDWINM and RLDICL.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
-rw-r--r-- | target/ppc/translate.c | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 59e9552d2b..435c6f0c63 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -1975,16 +1975,16 @@ static void gen_rlwinm(DisasContext *ctx) { TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; - uint32_t sh = SH(ctx->opcode); - uint32_t mb = MB(ctx->opcode); - uint32_t me = ME(ctx->opcode); - - if (mb == 0 && me == (31 - sh)) { - tcg_gen_shli_tl(t_ra, t_rs, sh); - tcg_gen_ext32u_tl(t_ra, t_ra); - } else if (sh != 0 && me == 31 && sh == (32 - mb)) { - tcg_gen_ext32u_tl(t_ra, t_rs); - tcg_gen_shri_tl(t_ra, t_ra, mb); + int sh = SH(ctx->opcode); + int mb = MB(ctx->opcode); + int me = ME(ctx->opcode); + int len = me - mb + 1; + int rsh = (32 - sh) & 31; + + if (sh != 0 && len > 0 && me == (31 - sh)) { + tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); + } else if (me == 31 && rsh + len <= 32) { + tcg_gen_extract_tl(t_ra, t_rs, rsh, len); } else { target_ulong mask; #if defined(TARGET_PPC64) @@ -1992,8 +1992,9 @@ static void gen_rlwinm(DisasContext *ctx) me += 32; #endif mask = MASK(mb, me); - - if (mask <= 0xffffffffu) { + if (sh == 0) { + tcg_gen_andi_tl(t_ra, t_rs, mask); + } else if (mask <= 0xffffffffu) { TCGv_i32 t0 = tcg_temp_new_i32(); tcg_gen_trunc_tl_i32(t0, t_rs); tcg_gen_rotli_i32(t0, t0, sh); @@ -2096,11 +2097,13 @@ static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) { TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; + int len = me - mb + 1; + int rsh = (64 - sh) & 63; - if (sh != 0 && mb == 0 && me == (63 - sh)) { - tcg_gen_shli_tl(t_ra, t_rs, sh); - } else if (sh != 0 && me == 63 && sh == (64 - mb)) { - tcg_gen_shri_tl(t_ra, t_rs, mb); + if (sh != 0 && len > 0 && me == (63 - sh)) { + tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); + } else if (me == 63 && rsh + len <= 64) { + tcg_gen_extract_tl(t_ra, t_rs, rsh, len); } else { tcg_gen_rotli_tl(t_ra, t_rs, sh); tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); |