diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2017-04-20 17:32:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-04-20 17:39:17 +0100 |
| commit | bedb8a6b09c1754c3b9f155750c62dc087706698 (patch) | |
| tree | 65fc7dc586524e4682cc59d5dcf13310f5d5649f /target | |
| parent | 9d7c59c84d4530d05e8702b1c3a31e6da00a397e (diff) | |
arm: Thumb shift operations should not permit interworking branches
In Thumb mode, the only instructions which can cause an interworking
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
ARM mode, data processing instructions which target the PC do not
cause interworking branches.
When we added support for doing interworking branches on writes to
PC from data processing instructions in commit 21aeb3430ce7ba, we
accidentally changed a Thumb instruction to have interworking
branch behaviour for writes to PC. (MOV, MOVS register-shifted
register, encoding T2; this is the standard encoding for
LSL/LSR/ASR/ROR (register).)
For this encoding, behaviour with Rd == R15 is specified as
UNPREDICTABLE, so allowing an interworking branch is within
spec, but it's confusing and differs from our handling of this
class of UNPREDICTABLE for other Thumb ALU operations. Make
it perform a simple (non-interworking) branch like the others.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 1491844419-12485-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index fe3f44298c..ddc62b6f0b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9959,7 +9959,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw gen_arm_shift_reg(tmp, op, tmp2, logic_cc); if (logic_cc) gen_logic_CC(tmp); - store_reg_bx(s, rd, tmp); + store_reg(s, rd, tmp); break; case 1: /* Sign/zero extend. */ op = (insn >> 20) & 7; |