diff options
| author | Craig Janeczek <jancraig@amazon.com> | 2018-10-18 14:36:57 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-29 14:13:47 +0100 |
| commit | a031ac61619294ae473a78d1834e757fad8b59e5 (patch) | |
| tree | 6c6adf2a2d3dac159737d8e5a9ba2223dd986b4c /target | |
| parent | eb5559f67dc8dc12335dd996877bb6daaea32eb2 (diff) | |
target/mips: Define a bit for MXU in insn_flags
Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/mips-defs.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 5177618615..dbdb4b2b2d 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -69,6 +69,7 @@ * bits 56-63: vendor-specific ASEs */ #define ASE_MMI 0x0100000000000000ULL +#define ASE_MXU 0x0200000000000000ULL /* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1) |