diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2023-11-04 21:44:01 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-06-05 09:10:02 -0700 |
| commit | 56f2ef9c7958320d574448f555cc3a82e500c485 (patch) | |
| tree | 35e26c8b8c4fc3b581d180158d0a6b65ea7805c4 /target | |
| parent | db11dfea83e35c534fef8a86603b72354be9d71b (diff) | |
target/sparc: Implement SUBXC, SUBXCcc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/sparc/insns.decode | 2 | ||||
| -rw-r--r-- | target/sparc/translate.c | 14 |
2 files changed, 16 insertions, 0 deletions
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 2ebee5a1ca..a7720560f8 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -447,6 +447,8 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \ PDISTN 10 ..... 110110 ..... 0 0011 1111 ..... @r_d_d FMEAN16 10 ..... 110110 ..... 0 0100 0000 ..... @d_d_d + SUBXC 10 ..... 110110 ..... 0 0100 0001 ..... @r_r_r + SUBXCcc 10 ..... 110110 ..... 0 0100 0011 ..... @r_r_r FCHKSM16 10 ..... 110110 ..... 0 0100 0100 ..... @d_d_d FALIGNDATAg 10 ..... 110110 ..... 0 0100 1000 ..... @d_d_d FPMERGE 10 ..... 110110 ..... 0 0100 1011 ..... @d_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 5bed23a00b..b10936a61a 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -515,6 +515,17 @@ static void gen_op_subccc(TCGv dst, TCGv src1, TCGv src2) gen_op_subcc_int(dst, src1, src2, gen_carry32()); } +static void gen_op_subxc(TCGv dst, TCGv src1, TCGv src2) +{ + tcg_gen_sub_tl(dst, src1, src2); + tcg_gen_sub_tl(dst, dst, cpu_cc_C); +} + +static void gen_op_subxccc(TCGv dst, TCGv src1, TCGv src2) +{ + gen_op_subcc_int(dst, src1, src2, cpu_cc_C); +} + static void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) { TCGv zero = tcg_constant_tl(0); @@ -3963,6 +3974,9 @@ TRANS(ARRAY32, VIS1, do_rrr, a, gen_op_array32) TRANS(ADDXC, VIS3, do_rrr, a, gen_op_addxc) TRANS(ADDXCcc, VIS3, do_rrr, a, gen_op_addxccc) +TRANS(SUBXC, VIS4, do_rrr, a, gen_op_subxc) +TRANS(SUBXCcc, VIS4, do_rrr, a, gen_op_subxccc) + TRANS(UMULXHI, VIS3, do_rrr, a, gen_op_umulxhi) static void gen_op_alignaddr(TCGv dst, TCGv s1, TCGv s2) |