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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-03-05 16:09:21 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-03-05 16:09:21 +0000 |
| commit | 597d61a3b1f94c53a3aaa77671697c0c5f797dbf (patch) | |
| tree | eaec38685831746aa3d8b84059f7c5ad5bb3d501 /target | |
| parent | 1371b02c5a060e423e70560dbca769b54e471ba9 (diff) | |
target/arm: Clean address for DC ZVA
This data access was forgotten when we added support for cleaning
addresses of TBI information.
Fixes: 3a471103ac1823ba
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200302175829.2183-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate-a64.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c910a49b4e..fefe8af7f5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1784,7 +1784,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. */ - tcg_rt = cpu_reg(s, rt); + tcg_rt = clean_data_tbi(s, cpu_reg(s, rt)); gen_helper_dc_zva(cpu_env, tcg_rt); return; default: |