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authorPaolo Bonzini <pbonzini@redhat.com>2023-04-03 19:28:36 +0200
committerPaolo Bonzini <pbonzini@redhat.com>2023-04-20 11:17:35 +0200
commitdfae46c3ba4880036a3df0b0aafca0c792b7cb9d (patch)
treef43e30b2d4ceb4eb332783388c1597bca7db6d4e /target
parentcc03dfa827819c78fdc6c8c5065910d6ac2567f1 (diff)
target/mips: tcg: detect out-of-bounds accesses to cpu_gpr and cpu_gpr_hi
In some cases (for example gen_compute_branch_nm in nanomips_translate.c.inc) registers can be unused on some paths and a negative value is passed in that case: gen_compute_branch_nm(ctx, OPC_BPOSGE32, 4, -1, -2, imm << 1); To avoid an out of bounds access in those cases, introduce assertions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/mips/tcg/translate.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 1fb4ef7127..999fbb7cc1 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -1223,6 +1223,7 @@ static const char regnames_LO[][4] = {
/* General purpose registers moves. */
void gen_load_gpr(TCGv t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
if (reg == 0) {
tcg_gen_movi_tl(t, 0);
} else {
@@ -1232,6 +1233,7 @@ void gen_load_gpr(TCGv t, int reg)
void gen_store_gpr(TCGv t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr));
if (reg != 0) {
tcg_gen_mov_tl(cpu_gpr[reg], t);
}
@@ -1240,6 +1242,7 @@ void gen_store_gpr(TCGv t, int reg)
#if defined(TARGET_MIPS64)
void gen_load_gpr_hi(TCGv_i64 t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi));
if (reg == 0) {
tcg_gen_movi_i64(t, 0);
} else {
@@ -1249,6 +1252,7 @@ void gen_load_gpr_hi(TCGv_i64 t, int reg)
void gen_store_gpr_hi(TCGv_i64 t, int reg)
{
+ assert(reg >= 0 && reg <= ARRAY_SIZE(cpu_gpr_hi));
if (reg != 0) {
tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
}