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authorGustavo Romero <gustavo.romero@linaro.org>2024-06-24 18:09:15 +0000
committerPeter Maydell <peter.maydell@linaro.org>2024-07-01 15:40:53 +0100
commit02ff2add77099f9deb7d6a18c9b4110572771f6a (patch)
tree7373cd9cb16870b04158ee0f9a056f5f70fcc859 /target
parentc5f9e8bb9300d0cae42d2cb19f6a4d340813f8b5 (diff)
target/arm: Enable FEAT_Debugv8p8 for -cpu max
Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU since it concerns the external debug interface for JTAG, but is mandatory in Armv8.8 implementations, hence it is reported as supported in the ID registers. Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240624180915.4528-4-gustavo.romero@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/tcg/cpu32.c6
-rw-r--r--target/arm/tcg/cpu64.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c
index 28a5c033bb..20c2737f17 100644
--- a/target/arm/tcg/cpu32.c
+++ b/target/arm/tcg/cpu32.c
@@ -82,8 +82,8 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_pfr2 = t;
t = cpu->isar.id_dfr0;
- t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
- t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP32(t, ID_DFR0, COPDBG, 10); /* FEAT_Debugv8p8 */
+ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
cpu->isar.id_dfr0 = t;
@@ -93,7 +93,7 @@ void aa32_max_features(ARMCPU *cpu)
t = 0x00008000;
t = FIELD_DP32(t, DBGDIDR, SE_IMP, 1);
t = FIELD_DP32(t, DBGDIDR, NSUHD_IMP, 1);
- t = FIELD_DP32(t, DBGDIDR, VERSION, 6); /* Armv8 debug */
+ t = FIELD_DP32(t, DBGDIDR, VERSION, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP32(t, DBGDIDR, CTX_CMPS, 1);
t = FIELD_DP32(t, DBGDIDR, BRPS, 5);
t = FIELD_DP32(t, DBGDIDR, WRPS, 3);
diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c
index 71e1bfcd4e..fe232eb306 100644
--- a/target/arm/tcg/cpu64.c
+++ b/target/arm/tcg/cpu64.c
@@ -1253,7 +1253,7 @@ void aarch64_max_tcg_initfn(Object *obj)
cpu->isar.id_aa64zfr0 = t;
t = cpu->isar.id_aa64dfr0;
- t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */
+ t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 10); /* FEAT_Debugv8p8 */
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */
t = FIELD_DP64(t, ID_AA64DFR0, HPMN0, 1); /* FEAT_HPMN0 */
cpu->isar.id_aa64dfr0 = t;