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authorPeter Maydell <peter.maydell@linaro.org>2021-11-01 16:08:14 +0000
committerRichard Henderson <richard.henderson@linaro.org>2021-11-02 14:14:55 -0400
commitdbd9e08476f09cf3556b9b8a306bf277172841a9 (patch)
treebbf2e9e9627b6b33a9d4d6a731e8027559891b75 /target
parentda2f02b360f405d7badc4a3028276e07db58026c (diff)
target/arm: Advertise MVE to gdb when present
Cortex-M CPUs with MVE should advertise this fact to gdb, using the org.gnu.gdb.arm.m-profile-mve XML feature, which defines the VPR register. Presence of this feature also tells gdb to create pseudo-registers Q0..Q7, so we do not need to tell gdb about them separately. Note that unless you have a very recent GDB that includes this fix: http://patches-tcwg.linaro.org/patch/58133/ gdb will mis-print the individual fields of the VPR register as zero (but showing the whole thing as hex, eg with "print /x $vpr" will give the correct value). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211101160814.5103-1-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/gdbstub.c25
1 files changed, 25 insertions, 0 deletions
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index e0dcb33e32..134da0d0ae 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -199,6 +199,27 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
+static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)
+{
+ switch (reg) {
+ case 0:
+ return gdb_get_reg32(buf, env->v7m.vpr);
+ default:
+ return 0;
+ }
+}
+
+static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
+{
+ switch (reg) {
+ case 0:
+ env->v7m.vpr = ldl_p(buf);
+ return 4;
+ default:
+ return 0;
+ }
+}
+
/**
* arm_get/set_gdb_*: get/set a gdb register
* @env: the CPU state
@@ -468,6 +489,10 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2, "arm-vfp-sysregs.xml", 0);
}
}
+ if (cpu_isar_feature(aa32_mve, cpu)) {
+ gdb_register_coprocessor(cs, mve_gdb_get_reg, mve_gdb_set_reg,
+ 1, "arm-m-profile-mve.xml", 0);
+ }
gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,
arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),
"system-registers.xml", 0);