diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2022-10-01 07:09:33 -0700 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-10-11 09:36:01 +0200 |
| commit | f771ca6a6127cdbdf4ed119e9d6c63abdad24181 (patch) | |
| tree | 3f7ceb4a46a98eb34323d655c7d57f8cd62d5b5e /target | |
| parent | 75ec746a07b6db4c214102e644319a334c1ab899 (diff) | |
target/i386: Add cpu_eip
Create a tcg global temp for this, and use it instead of explicit stores.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20221001140935.465607-25-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/i386/tcg/translate.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5b0dab8633..f08fa060c4 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -64,6 +64,7 @@ /* global register indexes */ static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2; +static TCGv cpu_eip; static TCGv_i32 cpu_cc_op; static TCGv cpu_regs[CPU_NB_REGS]; static TCGv cpu_seg_base[6]; @@ -481,7 +482,7 @@ static void gen_add_A0_im(DisasContext *s, int val) static inline void gen_op_jmp_v(TCGv dest) { - tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip)); + tcg_gen_mov_tl(cpu_eip, dest); } static inline @@ -518,7 +519,7 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) static void gen_jmp_im(DisasContext *s, target_ulong pc) { - gen_op_jmp_v(tcg_constant_tl(pc)); + tcg_gen_movi_tl(cpu_eip, pc); } static void gen_update_eip_cur(DisasContext *s) @@ -8616,6 +8617,13 @@ void tcg_x86_init(void) [R_ESP] = "esp", #endif }; + static const char eip_name[] = { +#ifdef TARGET_X86_64 + "rip" +#else + "eip" +#endif + }; static const char seg_base_names[6][8] = { [R_CS] = "cs_base", [R_DS] = "ds_base", @@ -8640,6 +8648,7 @@ void tcg_x86_init(void) "cc_src"); cpu_cc_src2 = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_src2), "cc_src2"); + cpu_eip = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, eip), eip_name); for (i = 0; i < CPU_NB_REGS; ++i) { cpu_regs[i] = tcg_global_mem_new(cpu_env, |