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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-02-23 09:59:40 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-02-23 09:59:40 +0000 |
| commit | 10f25e4844cb9b3f02fb032f88051dd5b65b4206 (patch) | |
| tree | 5bdce6b6ff69db978cf419e8b78975f7cd338bb3 /target | |
| parent | e295a154c2a95f114e52ef4b0fb22b801b028bdc (diff) | |
| parent | d3473e147a754e999718bf6fcb015d9978c6a1ee (diff) | |
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170222' into staging
MIPS patches 2017-02-22
Changes:
* Add MIPS Boston board support
# gpg: Signature made Wed 22 Feb 2017 00:08:00 GMT
# gpg: using RSA key 0x2238EB86D5F797C2
# gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg: It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2
* remotes/yongbok/tags/mips-20170222:
hw/mips: MIPS Boston board support
hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller
loader: Support Flattened Image Trees (FIT images)
dtc: Update requirement to v1.4.2
target-mips: Provide function to test if a CPU supports an ISA
hw/mips_gic: Update pin state on mask changes
hw/mips_gictimer: provide API for retrieving frequency
hw/mips_cmgcr: allow GCR base to be moved
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/mips/cpu.h | 1 | ||||
| -rw-r--r-- | target/mips/translate.c | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index e1c78f55ec..4a4747af25 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -815,6 +815,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model)) bool cpu_supports_cps_smp(const char *cpu_model); +bool cpu_supports_isa(const char *cpu_model, unsigned int isa); void cpu_set_exception_base(int vp_index, target_ulong address); /* TODO QOM'ify CPU reset and remove */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 7f8ecf42c2..8b4a072ecb 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20233,6 +20233,16 @@ bool cpu_supports_cps_smp(const char *cpu_model) return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; } +bool cpu_supports_isa(const char *cpu_model, unsigned int isa) +{ + const mips_def_t *def = cpu_mips_find_by_name(cpu_model); + if (!def) { + return false; + } + + return (def->insn_flags & isa) != 0; +} + void cpu_set_exception_base(int vp_index, target_ulong address) { MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); |