diff options
author | Richard Henderson <rth@twiddle.net> | 2015-02-18 12:34:56 -0800 |
---|---|---|
committer | Richard Henderson <rth@twiddle.net> | 2017-02-14 08:14:59 +1100 |
commit | 0c53d7342b4e8412f3b81eed67f053304813dc5d (patch) | |
tree | df1313a2cc5750bc9801b953072afab91d836248 /target | |
parent | 9ecaa27e7123211f45ca723a736ffae14f6c1f42 (diff) |
target/openrisc: Put SR[OVE] in TB flags
Removes a call at execution time for overflow exceptions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'target')
-rw-r--r-- | target/openrisc/cpu.h | 4 | ||||
-rw-r--r-- | target/openrisc/exception_helper.c | 2 | ||||
-rw-r--r-- | target/openrisc/translate.c | 24 |
3 files changed, 18 insertions, 12 deletions
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 06d0e897d8..ef90e49a4d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -400,8 +400,8 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, { *pc = env->pc; *cs_base = 0; - /* D_FLAG -- branch instruction exception */ - *flags = (env->flags & D_FLAG); + /* D_FLAG -- branch instruction exception, OVE overflow trap enable. */ + *flags = (env->flags & D_FLAG) | (env->sr & SR_OVE); } static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch) diff --git a/target/openrisc/exception_helper.c b/target/openrisc/exception_helper.c index 7e54c978be..5147da68c4 100644 --- a/target/openrisc/exception_helper.c +++ b/target/openrisc/exception_helper.c @@ -32,7 +32,7 @@ void HELPER(exception)(CPUOpenRISCState *env, uint32_t excp) void HELPER(ove)(CPUOpenRISCState *env, target_ulong test) { - if (unlikely(test) && (env->sr & SR_OVE)) { + if (unlikely(test)) { OpenRISCCPU *cpu = openrisc_env_get_cpu(env); CPUState *cs = CPU(cpu); diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c6cd1c1db..b8116bae86 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -132,8 +132,8 @@ static inline void wb_SR_F(void) static inline void gen_sync_flags(DisasContext *dc) { /* Sync the tb dependent flag between translate and runtime. */ - if (dc->tb_flags != dc->synced_flags) { - tcg_gen_movi_tl(env_flags, dc->tb_flags); + if ((dc->tb_flags ^ dc->synced_flags) & D_FLAG) { + tcg_gen_movi_tl(env_flags, dc->tb_flags & D_FLAG); dc->synced_flags = dc->tb_flags; } } @@ -249,20 +249,26 @@ static void gen_jump(DisasContext *dc, int32_t n26, uint32_t reg, uint32_t op0) static void gen_ove_cy(DisasContext *dc, TCGv cy) { - gen_helper_ove(cpu_env, cy); + if (dc->tb_flags & SR_OVE) { + gen_helper_ove(cpu_env, cy); + } } static void gen_ove_ov(DisasContext *dc, TCGv ov) { - gen_helper_ove(cpu_env, ov); + if (dc->tb_flags & SR_OVE) { + gen_helper_ove(cpu_env, ov); + } } static void gen_ove_cyov(DisasContext *dc, TCGv cy, TCGv ov) { - TCGv t0 = tcg_temp_new(); - tcg_gen_or_tl(t0, cy, ov); - gen_helper_ove(cpu_env, t0); - tcg_temp_free(t0); + if (dc->tb_flags & SR_OVE) { + TCGv t0 = tcg_temp_new(); + tcg_gen_or_tl(t0, cy, ov); + gen_helper_ove(cpu_env, t0); + tcg_temp_free(t0); + } } static void gen_add(DisasContext *dc, TCGv dest, TCGv srca, TCGv srcb) @@ -1606,7 +1612,7 @@ void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb) dc->flags = cpu->env.cpucfgr; dc->mem_idx = cpu_mmu_index(&cpu->env, false); dc->synced_flags = dc->tb_flags = tb->flags; - dc->delayed_branch = !!(dc->tb_flags & D_FLAG); + dc->delayed_branch = (dc->tb_flags & D_FLAG) != 0; dc->singlestep_enabled = cs->singlestep_enabled; next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; |