diff options
| author | LIU Zhiwei <zhiwei_liu@linux.alibaba.com> | 2023-12-15 10:33:13 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-01-10 18:47:46 +1000 |
| commit | 7767f8b122dc061f9a68802b41b82117e755b03a (patch) | |
| tree | 56e42061f19e84799c1c130526918bc44785c8f7 /target | |
| parent | 564a28bda1b06eb54dc555c0e34403c6f5657a00 (diff) | |
target/riscv: Not allow write mstatus_vs without RVV
If CPU does not implement the Vector extension, it usually means
mstatus vs hardwire to zero. So we should not allow write a
non-zero value to this field.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231215023313.1708-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/csr.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c50a33397c..d8f751a0ae 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1328,11 +1328,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno, mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | - MSTATUS_TW | MSTATUS_VS; + MSTATUS_TW; if (riscv_has_ext(env, RVF)) { mask |= MSTATUS_FS; } + if (riscv_has_ext(env, RVV)) { + mask |= MSTATUS_VS; + } if (xl != MXL_RV32 || env->debugger) { if (riscv_has_ext(env, RVH)) { |