diff options
author | Richard Henderson <richard.henderson@linaro.org> | 2023-10-10 14:56:49 -0700 |
---|---|---|
committer | Richard Henderson <richard.henderson@linaro.org> | 2023-10-25 01:01:13 -0700 |
commit | 8aa418b3ef1b261757408642385dd8fd62bffb36 (patch) | |
tree | e21c142e950d12601a0229ebbab9f72c753b30e7 /target | |
parent | 119cb94f69e2180f1a8685b53a0659f195bdd90c (diff) |
target/sparc: Move gen_fop_DD insns to decodetree
Move FSQRTd, FxTOd, FdTOx.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r-- | target/sparc/insns.decode | 3 | ||||
-rw-r--r-- | target/sparc/translate.c | 50 |
2 files changed, 30 insertions, 23 deletions
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 85464285b7..1d766fab21 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -246,6 +246,9 @@ FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2 FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 +FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 +FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 +FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 FsTOi 10 ..... 110100 00000 0 1101 0001 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 13932e087d..307fbc4628 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -63,6 +63,7 @@ # define gen_helper_write_softint(E, S) qemu_build_not_reached() # define gen_helper_wrpil(E, S) qemu_build_not_reached() # define gen_helper_wrpstate(E, S) qemu_build_not_reached() +# define gen_helper_fdtox ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fexpand ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8sux16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmul8ulx16 ({ qemu_build_not_reached(); NULL; }) @@ -72,6 +73,7 @@ # define gen_helper_fmuld8sux16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fmuld8ulx16 ({ qemu_build_not_reached(); NULL; }) # define gen_helper_fpmerge ({ qemu_build_not_reached(); NULL; }) +# define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; }) # define gen_helper_pdist ({ qemu_build_not_reached(); NULL; }) # define FSR_LDXFSR_MASK 0 # define FSR_LDXFSR_OLDMASK 0 @@ -1669,20 +1671,6 @@ static void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_F(dc, rd, dst); } -static void gen_fop_DD(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64)) -{ - TCGv_i64 dst, src; - - src = gen_load_fpr_D(dc, rs); - dst = gen_dest_fpr_D(dc, rd); - - gen(dst, tcg_env, src); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_store_fpr_D(dc, rd, dst); -} - static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64)) { @@ -4835,6 +4823,28 @@ TRANS(FABSd, 64, do_dd, a, gen_op_fabsd) TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64) TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64) +static bool do_env_dd(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_i64, TCGv_env, TCGv_i64)) +{ + TCGv_i64 dst, src; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + dst = gen_dest_fpr_D(dc, a->rd); + src = gen_load_fpr_D(dc, a->rs); + func(dst, tcg_env, src); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_store_fpr_D(dc, a->rd, dst); + return advance_pc(dc); +} + +TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) +TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) +TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -4977,10 +4987,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x29: /* fsqrts */ case 0xc4: /* fitos */ case 0xd1: /* fstoi */ - g_assert_not_reached(); /* in decodetree */ case 0x2a: /* fsqrtd */ - gen_fop_DD(dc, rd, rs2, gen_helper_fsqrtd); - break; + case 0x82: /* V9 fdtox */ + case 0x88: /* V9 fxtod */ + g_assert_not_reached(); /* in decodetree */ case 0x2b: /* fsqrtq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); @@ -5085,9 +5095,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x81: /* V9 fstox */ gen_fop_DF(dc, rd, rs2, gen_helper_fstox); break; - case 0x82: /* V9 fdtox */ - gen_fop_DD(dc, rd, rs2, gen_helper_fdtox); - break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_fop_DQ(dc, rd, rs2, gen_helper_fqtox); @@ -5095,9 +5102,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x84: /* V9 fxtos */ gen_fop_FD(dc, rd, rs2, gen_helper_fxtos); break; - case 0x88: /* V9 fxtod */ - gen_fop_DD(dc, rd, rs2, gen_helper_fxtod); - break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_ne_fop_QD(dc, rd, rs2, gen_helper_fxtoq); |