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authorAtish Patra <atishp@rivosinc.com>2022-03-03 10:54:36 -0800
committerAlistair Francis <alistair.francis@wdc.com>2022-04-22 10:35:16 +1000
commit3a4af26d7a821b0299d25a2b002455899f1303ff (patch)
treef03805b92f8d97531585dc056c38132aaab89808 /target
parenta46d410c5c19fa752d0ba03333e70170b8a6f57a (diff)
target/riscv: Add the privileged spec version 1.12.0
Add the definition for ratified privileged specification version v1.12 Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220303185440.512391-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 345ec2c773..19c3b6610b 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -86,6 +86,7 @@ enum {
enum {
PRIV_VERSION_1_10_0 = 0,
PRIV_VERSION_1_11_0,
+ PRIV_VERSION_1_12_0,
};
#define VEXT_VERSION_1_00_0 0x00010000